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ao486: x86-compatible Verilog core implementing all features of a 486 SX (2014)
I designed a nibble-oriented CPU in Verilog to build a scientific calculator
A Verilog to Factorio Compiler and Simulator (Working RISC-V CPU)
OpenSERDES – Open Hardware Serializer/Deserializer (SerDes) in Verilog (2020)
Automated feature testing of Verilog parsers using fuzzing
Tiny GPU: A minimal GPU implementation in Verilog
