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Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool
Democratizing silicon
Cambridge, MA – September 17, 2025 – Zero ASIC, a U.S. semiconductor startup on a mission to democratize silicon, today announced the release of Wildebeest TM, the world’s highest performance FPGA synthesis tool. Thanks to the pioneering work of Alan Mishchenko (ABC 2), Claire Xenia Wolf (Yosys 3), and the broader open source EDA community, FPGA developers have had access to a full-featured Verilog RTL synthesis toolchain for years. The long term goal of the Wildebeest project is to help bring forth an era of “LLVM for synthesis” by working with the community to develop high performance open source FPGA tools, robust standard IRs and file formats, and broad hardware vendor adoption.
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