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6th generation x86 CPU Comparisons

Paul Hsieh's 6th generation x86 CPU comparision page including K6, P-II and 6x86MX geared towards the high performance software developer audience

Although it is not as well described, I believe that Intel's reservation station and reorder buffer combinations serves substantially the same purpose as the K6's scheduler, and similarly the retire unit acts on instruction clusters in exactly the same way as they were issued (CPUs are not otherwise known to have sorting algorithms wired into them.) As another example, highly complex (compiled) applications that weave together the resources of many code paths (web browsers, office suite packages, and pre-emptive multitasking OSes in general) would prefer to have larger instruction caches. Post-RISC architecture- a term coined by Charles Severance referring to the modern trend of CPUs to use techniques not found on traditional RISC processors such as speculative execution and register renaming in conjunction with instruction retirement.

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