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AMD's Strix Halo under the hood

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George Cozma: Now moving from the CPU over to the big huge SOC tile over here that holds your iGPU, now I know that this wasn't mentioned in the slide deck, but there's 32 megabytes of what's known as MALL or infinity cache. George Cozma: It's not the point of coherency and speaking to again to the data fabric, are you seeing any clock speed benefit from the fact that it's just a sea of wires connecting the CPU to the SOC tile? George Cozma: And so sort of to end this conversation back where we started at the CPU with that fabric, how much memory bandwidth can the single CCD access since it is 32 bytes per cycle reads?

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