Get the latest tech news
Baby Steps Toward 3D DRAM
Stacking layers means a complete architecture rethink.
“Most recent steps toward footprint reduction pit EUV patterning against traditional ArF SADP and SAQP processes for cutting-edge 2D DRAM nodes,” said Daniel Soden, business development manager at Brewer Science. The challenge with this approach is that it requires multiple word lines to set up the polarity of the various regions along a horizontal piece of silicon to create the PNPN structure. “However, it did not successfully enter mass production because of challenges related to data retention, leakage currents, and difficulty in controlling the floating body potential, especially when scaling down to smaller cell sizes.
Or read this on r/technology