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Distance-Based ISA for Efficient Register Management
CPU cores have become significantly wider over the past decade. Ten years ago, the highest-performance CPUs could decode only up to four instructions simultaneously and execute up to eight instruct…
RISC-V is often considered a definitive RISC instruction set, as it was carefully designed to avoid past pitfalls, such as reliance on specific hardware characteristics (e.g., delay slots), which have limited the scalability of previous architectures. Unlike CPUs, GPU programs are typically distributed in an intermediate representation (such as PTX for NVIDIA GPUs or SPIR-V for Vulkan), which is then translated by drivers into the appropriate internal instruction set for the hardware. Research centers on hardware-software co-design and spans instruction set architecture, enhancements to out-of-order execution using advanced predictors, compiler construction for novel ISAs, arithmetic circuit design, and fast and accurate floating-point algorithms.
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