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Exploring the scalable matrix extension of the Apple M4 processor


Exploring the scalable matrix extension of the Apple M4 processor - tzakharko/m4-sme-exploration

The M4 chip with SME changes this by allowing programmers to write low-level code that directly targets the matrix hardware, bringing potential performance improvements to scientific and machine learning algorithms. SVE features 32 scalable SIMD registers (Z0-Z31) with VL (vector length) bits each, and SME adds a VLxVL two-dimensional tile storage called ZA. Instead, the "regular SVE" mode uses the CPU SIMD registers and execution units, which are more flexible but might have lower total compute capability and no advanced matrix support.

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