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Getting into way too much detail with the Z80 netlist simulation (2021)
TL;DR: a detailed look at Z80 instruction timings with the help of a Z80 netlist simulation.
In the first post I’ll mainly take a look at the oddities and irregularities in the Z80 instruction set with the help of the Z80 netlist simulation from visual6502.org which I integrated into my own ‘remix’ before starting to work on the actual CPU emulator: rendering and UI performance is much improved via WASM, WebGL and Dear ImGui an integrated assembler simplifies program input a tracelog window which shows more information and allows to ‘rewind’ the simulation Instructions which are reinterpreted from(HL) to(IX+d) or(IY+d) load an additional offset byte ‘d’ which is signed-added to IX or IY to form the effective address for the memory access.
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