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Hardware FPGA DPS-8M Mainframe and FNP Project
We’re excited to announce an ambitious long-term project, currently in the early stages, to implement as much of the DPS‑8/M mainframe architecture as possible using one (or more) FPGAs — with the ability to run the full Multics operating system — is now underway, led by Dean S. Anderson. In the early 1980s, Dean started as a computer operator at Gelco on a large Honeywell Series‑60 ∕ Level‑66 dual processor mainframe (eventually converted to a four processor DPS‑8) running GCOS‑3.
He also wrote a lot of software in C for automating factory floor operations and board assembly, and worked on other large projects, including networking a significant number of Level 6 minicomputers. Since I’ve always been interested in FPGA development (and previously played around with it a bit), I decided my long-term hobby project would be to implement the complete DPS‑8/M distributed processing mainframe architecture in one or more FPGAs. After some discussion, I decided that first implementing the FNP ( Front-end Network Processor) component, specifically, the DATANET 355(or DN355), also known as the DN6632(denoting it’s 32 KW of memory), would be the ideal starting point.
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