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Hazard3: 3-stage RV32IMACZb* processor with debug
3-stage RV32IMACZb* processor with debug. Contribute to Wren6991/Hazard3 development by creating an account on GitHub.
The example SoC integration shows how these components can be assembled to create a minimal system with a JTAG-enabled RISC-V processor, some RAM and a serial port. Recent versions of GCC seem to remove the fallback to the--with-arch architecture when there is no exact match, so if you are developing for multiple ISA variants then you need a fairly expansive multilib setup. OpenOCD's role is to translate the abstract debug commands issued by gdb, e.g. "set the program counter to address x", to more concrete operations, e.g. "shift this JTAG DR".
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