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How to Design an ISA

Over the past decade I have been involved in several projects that have designed either instruction set architecture (ISA) extensions or clean-slate ISAs for various kinds of processors (you will even find my name in the acknowledgments for the RISC-V spec, right back to the first public version). When I started, I had very little idea about what makes a good ISA, and, as far as I can tell, this is not formally taught anywhere.

C has large amounts of mutable state and a bolted-on concurrency model that relies on shared everything, locking, and, typically, small numbers of threads. Early AMD GPUs were very long instruction word (VLIW) architectures; modern ones are not but can still run shaders written for the older designs. Even if you do not make the arithmetic logic units (ALUs) the full width of the registers and take two cycles to push each half through the execution pipeline, you still save a lot of the bookkeeping overhead.

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