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How to improve the RISC-V specification
My main project is to create an executable spec of the Intel Architecture but, every now and then, I get to take a broader look at ISA specifications and think about the strengths and weaknesses of other ISA specs: what makes them work well; and what techniques they could borrow from other specifications. Earlier this month, someone asked me for my thoughts on the RISC-V specification and I thought that it would be useful to share what I found out.
To make a difference, you have to modify the architecture reference manual, the Spike simulator, the testsuite and the SAIL specification to use this data. Fortunately, the fix is easy: either split the SAIL spec into smaller pieces (e.g., one definition per file) or write a tool to do it for you. This has resulted in the current situation where the architecture specification is, in effect, scattered over four different artifacts and each downstream tool/library/application has to transcribe information from those sources instead of being able to use architect-provided machine-readable formats to generate the code instead.
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