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Impact of Low Temperatures on the 5nm SRAM Array Size and Performance

A new technical paper titled “Novel Trade-offs in 5 nm FinFET SRAM Arrays at Extremely Low Temperatures” was published by researchers at University of Stuttgart, IIT Kanpur, National Yang Ming Chiao Tung University, Khalifa University, and TU Munich. Abstract “Complementary metal–oxide–semiconductor (CMOS)-based computing promises drastic improvement in performance at extremely low temperatures (e.g., 77 K,... » read more

This work aims to reveal how extremely low temperature operations profoundly impact the existing well-known tradeoffs in SRAM-based memory arrays. To accomplish this, first, we measure and model the 5 nm fin field-effect transistors characteristics over a wide temperature range from 300 K down to 10 K. Next, we develop a framework to perform simulations on the SRAM array by varying the number of rows and columns for examining the influence of leakage current (I leak) and parasitic effects of bit line (BL) and word line (WL) on the size and performance of the SRAM array under extremely low temperatures. S. S. Parihar, G. Pahwa, B. Mohammad, Y. S. Chauhan and H. Amrouch, “Novel Trade-offs in 5 nm FinFET SRAM Arrays at Extremely Low Temperatures,” in IEEE Transactions on Quantum Engineering, vol.

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