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Intel Patents 'Software Defined Supercore'
Reverse Hyper-Threading?
You may like While it is technically possible to build an 8-way x86 CPU core (i.e., a superscalar x86 processor that can decode, issue, and retire up to 8 instructions per clock), but in practice, it has not been done because of front-end bottlenecks as well as diminishing returns in terms of performance increase amid significant, power and area costs. These modules use a reserved memory region — called the wormhole address space — for coordinating live-in/live-out data and sync operations to ensure that instructions from separate cores retire in the correct program order. Support by operating system is crucial as the OS dynamically decides when to migrate a thread into or out of super-core mode based on runtime conditions to balance performance and core availability.
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