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MIT engineers grow “high-rise” 3D chips. An electronic stacking technique could exponentially increase the number of transistors on chips, enabling more efficient AI hardware.
MIT researchers fabricated 3D chips with alternating layers of semiconducting material grown directly on top of each other. The method eliminates thick silicon between layers, leading to better and faster computation, for applications like more efficient AI hardware.
Now, MIT engineers have found a way around this hurdle, with a multilayered chip design that doesn’t require any silicon wafer substrates and works at temperatures low enough to preserve the underlying layer’s circuitry. In a study appearing today in the journal Nature, the team reports using the new method to fabricate a multilayered chip with alternating layers of high-quality semiconducting material grown directly on top of each other. “This breakthrough opens up enormous potential for the semiconductor industry, allowing chips to be stacked without traditional limitations,” says study author Jeehwan Kim, associate professor of mechanical engineering at MIT.
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