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More AMD Zen 5 Tuning/Optimizations Merged For The GCC 15 Compiler
Following yesterday's initial tuning of the 'znver5' target for the AMD Zen 5 CPUs with the GCC 15 compiler, several more rounds of compiler tuning/optimizations were merged for benefiting the Ryzen AI 300 series, Ryzen 9000 series desktops, and upcoming EPYC Turin processors.
This has potential of increasing register pressure but unlike while benchmarking znver1 tuning I did not noticed this actually causing problem on spec, so this patch bumps up reassociation width to 6 for everything except for integer vectors, where there are 4 units with typical latency of 1." These patches might also be picked up for the next GCC 14 point release in the coming months for reaching a stable compiler version soon. Once the Znver5 optimizations settle down I'll be through a fresh round of GCC compiler benchmarking the performance impact with current Ryzen 9000 series desktop processors.
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