Get the latest tech news
NAND Flash Targets 1k Layers
New techniques go beyond improved deposition and etching, but challenges stack up, too.
“Scaling the pitch of this charge trap architecture is a good way to improve capacitor density on the device without further increasing layer count,” said Brewer’s Soden. “Physical and thermal stress from the higher stack height can create additional challenges for lithography and other downstream processes,” noted Brewer’s Soden. Stack and repeat A final twist on adding layers provides something of an end-around, both physically and geopolitically, to the plodding progress made processing ever deeper holes.
Or read this on Hacker News