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OpenCores: A-Z80 CPU
date: Rewritten in pure Verilog, the CPU can now be used on both Altera and Xilinx devices! A-Z80 is a conceptual implementation of the venerable Zilog Z80 processor targeted to synthesize and run on a modern FPGA device. It differs from the existing (mostly Verilog) Z80 implementations in that it is designed from the ground-up through the schematics and low-level gates.
A-Z80 is a conceptual implementation of the venerable Zilog Z80 processor targeted to synthesize and run on a modern FPGA device. Cycle and bus accurate including the correct behavior of nWAIT and nBUSRQ All documented and undocumented opcodes, flags and registers, including R, WZ Following the actual arcitectural model down to the individual gates and registers for some modules Passes ZEXDOC and ZEXLL (except quirky OTIR/LDIR for IX,IY) Correct behavior of BIT n,(HL) to expose WZ All interrupts modes (IM0,IM1,IM2) Slow Model fMax is 18 MHz, could be run even faster when optimized Name: a-z80Created: Dec 12, 2014Updated: Sep 10, 2020SVN Updated: Jul 12, 2020SVN: Browse Latest version: download(might take a bit to start...)Statistics: ViewBugs: 4 reported / 2 solved
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