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OpenSERDES – Open Hardware Serializer/Deserializer (SerDes) in Verilog (2020)
Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology. - SparcLab/OpenSERDES
The Serializer and Deserializer blocks are coded in Verilog HDL and synthesized using Openlane tool mapped to Sky130 CMOS technology. Simulation results and associated gds, spice and netlist files are uploaded in Serializer and Deserializer folders respectively The CDR uses the data transitions to tune the clock frequency for proper decoding of received signal.
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