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Partitioning in the Chiplet Era
Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.
“Manufacturability and process optimization, maximized reuse to generate future SKUs, control over the micro-architecture, power delivery, communication between chiplets, data transfers — that information is needed for a given project, and forward-looking roadmaps drive decisions for partitioning.” But what’s happening is those same companies that were making fortunes building complex SoCs are jumping straight to the how, and they’re forgetting that intermediate step of what exactly needs to be done, and therefore the connection back to the why is lost. A changing industry with new silicon form factors and larger units of IP requires new architecture specifications to ensure the potential benefits aren’t lost due to unnecessary and avoidable non-differentiating fragmentation.”
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