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PCIe Endpoint on Xilinx 7-Series FPGAs with PCIe_2_1 Hard Block and GTP

PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers - regymm/pcie_7x

PCIe Endpoint on Xilinx 7-Series FPGAs using the PCIE_2_1 hard block and GTP transceivers. No proprietary Vivado IP cores! For PCIE_2_1 parameters and port definitions, please refer to UG477.

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