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RISC-V With Linux 6.18 Brings Support For MIPS Vendor Extensions
Back during the Linux 6.17 merge window the RISC-V changes were rejected as 'garbage' for being submitted too late in the merge window and with some code choices that upset Linus Torvalds
With lessons learned, the RISC-V changes for Linux 6.18 were submitted today during the first official day of this new kernel cycle. - An architecture-specific endianness swap macro set implementation, leveraging some dedicated RISC-V instructions for this purpose if they are available - The ability to identity and communicate to userspace the presence of a MIPS P8700-specific ISA extension, and to leverage its MIPS-specific PAUSE implementation in cpu_relax()
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