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SUS Lang: The SUS Hardware Description Language
A return to RTL for high-performance Hardware Designs
Its main goal is to be an intuitive and thin syntax for building netlists, such that traditional synthesis tools can still be used to analyze the resulting hardware. Easy Pipelining: Achieved through an orthogonal construct called "Latency Counting" that doesn't interfere with other features. Type safety with Bounded Integers Multi-Clock modules Formal Verification Integration Syntactic sugar for common constructs like valid signals, resets and submodule communication Moving some timing constraints to the source file
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