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Symbolic Reference and Hardware Models in Python
- The Traditional Hardware Design and Verification Flow - An Image Downscaler as Example Design - The Reference Model - The Micro-Architecture Model - Comparing the results - Conversion to Hardware - Combining symbolic models with random input generation - Specification changes - Things to experiment with… - Symbolic models are best for block or sub-block level modelling - Conclusion - References The Traditional Hardware Design and Verification Flow In a professional FPGA or ASIC development flow, multiple models are tested against each other to ensure that the final design behaves the way it should. Common models are: - a behavioral model that describes the functionality at the highest level These models can be implemented in Matlab, Python, C++ etc.
Let’s design a hardware module that is easy enough to not spend too much time on it for a blog post, but complex enough to illustrate the benefits of a symbolic model: an image downscaler. When modeling transformations that work at the picture level, it’s convenient to assume that there are no memory size constraints and that you can access all pixels at all times no matter where they are located in the image. It’s scary to make changes on a hardware design that has complex data management when corner case bugs take thousands of regression simulations to uncover.
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