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The 286's internal registers (2022)

LOADALL structure as described by Intel is this: Physical Address (Hex) Associated CPU Register 800-805 None 806-807 MSW 808-815 None 816-817 TR 818-819 Flag word 81A-81B IP 81C-81D LDT 81E-81F DS 820-821 SS 822-823 CS 824-825 ES 826-827 DI 828-829 SI 82A-82B BP 82C-82D SP 82E-82F BX 830-831 DX 832-833 CX 834-835 AX 836-83B ES descriptor cache 83C-841 CS descriptor cache 842-847 SS descriptor cache 848-84D DS descriptor cache 84E-853 GDTR 854-859 LDT descriptor cache 85A-85F IDTR 860-865 TSS descriptor cache The normally visible registers aren't of much interest. That includes the MSW and flags: LOADALL can't change any of the reserved bits, and can't clear the protected mode bit once it has been set.

By making every segment load cause a protection fault, and using LOADALL to update the descriptor caches, an operating system could in theory emulate the real mode behaviour. Reading out all of the values immediately after power-up would require a custom ROM, instead of the cheap trick I used (overwriting the BIOS entry point in shadow RAM). Another idea is to run one instruction again and again, starting from a defined state and each time resetting it at a different clock cycle to observe what happens when.

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