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The Alder Lake SHLX Anomaly
vian Barnes At the end of 2024, Harold Aptroot posted this: Apparently shlx is a "medium latency" (3 cycles) instruction on Alder Lake. My disappointment is immeasurable, and my day is ruined.
I was immediately nerd sniped because I am into low-level performance analysis, and I happen to own an Alder Lake laptop. They even document the exact instruction sequence used in their benchmark that measured the 3-cycle latency, with a sample nanoBench command to reproduce it. The 32-bit vs. 64-bit operand size distinction is especially surprising to me as SHLX only looks at the bottom 6 bits of the shift count.
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