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TSMC mulls massive 1000W-class multi-chiplet processors with 40X the performance of standard models | A 9.5x reticle size SiP on a massive substrate.
A 9.5x reticle size SiP on a massive substrate.
In an effort to meet demand, TSMC is enhancing its packaging capabilities to support significantly larger chip assemblies for high-performance computing and AI applications. In addition, embedded deep trench capacitors (eDTC/DTC), built directly into the interposer or silicon substrate, provide high-density decoupling (up to 2,500 nF/mm^2) to improve power stability by filtering voltage fluctuations close to the die and ensure reliable operation even under rapid workload changes. This embedded approach enables effective DVS and improved transient response, both of which are critical for managing power efficiency in complex, multi-core, or multi-die designs.
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