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TSMC Preps Cheaper 4nm N4C Process For 2025, Aiming For 8.5% Cost Reduction
by Anton Shilov on April 25, 2024 10:00 AM EST - Posted in - Semiconductors - TSMC - 4nm - N4 - N4C - TSMC Symposium 2024 While the bulk of attention on TSMC is aimed at its leading-edge nodes, such as N3E and N2, loads of chips will continue to be made using more mature and proven process technologies for years to come. Which is why TSMC has continued to refine its existing nodes, including its current-generation 5nm-class offerings.
While the bulk of attention on TSMC is aimed at its leading-edge nodes, such as N3E and N2, loads of chips will continue to be made using more mature and proven process technologies for years to come. Furthermore, with the same wafer-level defect density rate as N4P, N4C stands to offer even higher functional yields thanks to its die area reduction. While N3 is expected to be a successful family, the high costs of N3B have been an issue, and the generation is marked by diminishing performance and transistor density returns altogether.
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