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TSMC: Performance-Optimized 3nm N3P Process on Track for Mass Production This Year
by Anton Shilov on May 15, 2024 6:00 PM EST As part of the second leg of TSMC's spring technology symposium series, the company offered an update on the state of its 3nm-class processes, both current and future. Building on the back of their current-generation N3E process, the optical shrink of this process technology, N3P, is now on track to enter mass production in the second half of 2024.
As part of the second leg of TSMC's spring technology symposium series, the company offered an update on the state of its 3nm-class processes, both current and future. Being an optical shrink, the N3P node is set to enable processor developers to either increase performance by 4% at the same leakage or reduce power consumption by 9% at the same clocks (previously the range was between 4% ~ 10% depending on design). The new node is also set to boost transistor density by 4% for a 'mixed' chip design, which TSMC defines as a processor consisting of 50% logic, 30% SRAM, and 20% analog circuits.
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