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Verifying FPGA using Free OS tools and frameworks
When working with FPGA, before we put the design on hardware we need to be able to verify it lets take a look at how we can do this. By Adam Taylor.
Indeed we have looked at one of these in a past project COCOTB which allows us to use Python to test our Verilog and VHDL using either commercial or open source simulators. This frame work provides a range of features from bus functional models for commonly used interfaces such as AXI, Wishbone, GMII, Ethernet, UART, SPI, and I2C etc. Traditionally, creating VHDL-based testbenches required significant effort, often leading to ad hoc, non-reusable, and hard-to-maintain code.
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