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What Microchip doesn't (officially) tell you about the VSC8512

witch project, part 3 - what Microchip doesn't (officially) tell you about the VSC8512 This is part 3 of my ongoing series about LATENTRED, my project to create an open source 1U managed Ethernet switch from scratch. Here’s a quick, or maybe not-so-quick, update about the PHY on the line card and some of my troubles (and solutions).

The eye was still reasonably open as-is and my cables and boards didn’t have a ton of insertion loss, so worst case things would probably work with the default TX config. Between the various documents I was able to conclude that the VSC8512 is made on an unspecified 65nm process (I should decap one at some point and figure out whose / see what it looks like… Luton first stepping is mentioned as being fabbed at TSMC in vtss_phy_do_page_chk so I suspect the rest are as well). Of note is that this SERDES offers more knobs on the output driver than most: slew rate control is rare on IOs of this class (most just run as fast as possible all the time), and most TX FFEs only have a single post-cursor tap, while this one has two.

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